74LS90 function: decimal counter (÷2 and ÷5)
Principle Description: This circuit consists of four master-slave flip-flops and an additional strobe used as a divide-by-2 counter and a 3-bit binary counter with a count period of five. There are strobe zero reset and set 9 inputs.
To take advantage of the maximum count length (decimal) of this counter, the B input can be connected to the QA output, and the input count pulse can be applied to input A, at which point the output is as required on the corresponding menu.
The LS90 can obtain a symmetrical ten-frequency count by connecting the QD output to the A input and applying the input count pulse to the B input to produce a symmetric ten-frequency square wave at the QA output.
Truth table:
Reset Inputs Reset Input Output R0(1) R0(2) R9(1) R9(2) QD QC QB QA HHLXLLLLHHXLLLLLXXHHH L LH XLXL
COUNT
COUNT
COUNT
COUNT
LXLXLXXLXLLX
H = high level L = low level × = indefinite
BCD counting order (Note 1)
Count
Output
QD QC QB QA 0 LLLL 1 LLLH 2 LLHL 3 LLHH 4 LHLL 5 LHLH 6 LHHL 7 LHHH 8 HLLL 9 HLLH
5-2 hex count order (Note 2)
Count
Output
QA QD QC QB 0 LLLL 1 LLLH 2 LLHL 3 LLHH 4 LHLL 5 HLLL 6 HLLH 7 HLHL 8 HLHH 9 HHLL
Note 1: For BCD (decimal) count, output QA is connected to input B count
Note 2: For 5-2 hex count, output QD is connected to input A count
Note 1: For BCD (decimal) count, output QA is connected to input B count
Note 2: For 5-2 hex count, output QD is connected to input A count
Figure 1 74LS90 pin diagram
Figure 2 74LS90 logic diagram
Recommended Operating Conditions Recommended Operating Conditions:
Symbol Symbol Parameter Parameter Minimum Typical Maximum UNIT Unit VCCSupply Voltage Power Supply Voltage 4.7555.25VVIHHigh Level Input Voltage Input High Level Voltage 2--VVILLOW Level Input Voltage Input Low Level Voltage--0.8VIOHHIGH Level Output Current High Level Output Current-- -0.4mAIOLLOW Level Output Current Low Level Output Current --8mAfCLKClock Frequency (Note 5) Clock Frequency A to QA0-32MHzB to QB0-16fCLKClock Frequency (Note 6) Clock Frequency A to QA0-20MHzB to QB0-10tWPulse Width (Note 5 Pulse width A15--nsB30--Reset15--tWPulse Width (Note 6) Pulse width A25--nsB50--Reset25--tRELReset Release Time (Note 5) Reset release time 25--nstRELReset Release Time (Note 6) Reset Release Time 35--nsTAFree Air Operating Temperature Operating Temperature 0-70°CNote 5: CL = 15 pF, RL = 2 kW, TA = 25°C and VCC = 5VNote 6: CL = 50 pF, RL = 2 kW, TA = 25°C and VCC = 5V
Electrical Characteristics Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Symbol Parameter Condition Conditions Minimum Typical Maximum UNIT Unit VIInput Clamp Voltage Input Clamp Voltage VCC = Minimum, II = -18mA---1.5VVOHHIGH Level Output Voltage Output high level voltage VCC=minimum, IOH=maximum VIL=max, VIH=min 2.73.4-VVOLLOW LevelOutput Voltage output low level voltage VCC = minimum, IOL = maximum VIL = maximum, VIH = minimum (Note 8)- 0.350.5VIOL= 4mA, VCC = minimum -0.250.4IIInput Current @ MAX Input Voltage Input Current @Maximum Input Voltage VCC = Maximum, VI =7VReset--0.1mAVCC = Maximum VI =5.5VA--0.2B--0.4IIHHIGH Level Input Current input high level current VCC = maximum, VI = 2.7VReset--20μAA--40B--80IILLOW LevelInput Current input low level current VCC = maximum, VI =0.4VReset---0.4mAA---2.4B- --3.2IOSShort Circuit Output Current Short Circuit Output Current VCC = Maximum (Note 9)-20--100mAICCSupply Current Supply Current VCC = Maximum (Note 7)-915mA
AC electrical characteristics:
Symbol Symbol Parameter Parameter To (Output)RL=2KUNIT Unit CL =15pFCL =50pF Min.Maximum Min Max fMaxMaximum Clock FrequencyMaximum Clock Frequency A to QA32-20-MHzB to QB16-10-tPLHPropagation Delay Time LOW-to-HIGH Level Output Low High-level output transfer delay time A to QA-16-20nstPHLPropagation Delay Time HIGH-to-LOW Level Output High-to-low output transfer delay time A to QA-18-24nstPLHPropagation Delay Time LOW-to-HIGH Level Output Low High-level output transfer delay time A to QD-48-52nstPHLPropagation Delay Time HIGH-to-LOW Level Output High-to-low output delivery delay time A to QD-50-60nstPLHPropagation Delay Time LOW-to-HIGH Level Output Low High-level output transfer delay time B to QB-16-23nstPHLPropagation Delay Time HIGH-to-LOW Level Output High-to-low output transfer delay time B to QB-21-30nstPLHPropagation Delay Time LOW-to-HIGH Level Output Low High level output transfer delay time
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