There are five common configuration modes for Spartan6 series FPGAs, which are determined by mode input pins M1 and M0. The five modes are detailed below.
The five modes can be divided into three categories, 1. JTAG mode (can be classified as slave mode); 2. main mode; 3. slave mode.
The main mode is divided into master serial mode and master parallel mode, and the slave mode is divided into slave serial mode.
There are two slave parallel modes. According to the interface of the platform flash chip, the main mode can be subdivided into the following four types.
(1) Four configuration modes of the main mode
(2) 3 modes of slave mode
Summary 1. When designing the circuit diagram, in order to choose the optimal FPGA configuration scheme, the following four aspects should be considered: overall settings, download rate, cost, and configuration flexibility.
2. In the main mode, the FPGA automatically loads the configuration file data, which is stored in the onboard ROM. In the slave mode, the configuration file data is loaded into the FPGA through the external MCU/processor.
3. The dedicated pin used as the configuration FPGA cannot be used as a normal IO pin after the configuration is completed, and the non-dedicated pin is released after the configuration is completed. It can be used as a normal IO pin.
4. When designing the circuit, be sure to set the correct level for the M1M0 pin. In order to expand the need or temporarily determine which configuration mode to select for the FPGA, the M1M0 pin can be reserved with pull-up and pull-down resistors for flexible selection.
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