MOSFET - Hot Swap Principle

When the power supply is suddenly disconnected from its load, large current swings on the parasitic inductance components of the circuit can create large spikes that can adversely affect the electronic components on the circuit. Similar to battery protection applications, the MOSFET here isolates the input supply from other circuits. But at this point, the role of the FET is not to immediately disconnect the input and output, but to mitigate the serious consequences of those damaging surge currents. This requires a controller to regulate the gate-to-source bias on the MOSFET between the input voltage (VIN) and the output voltage (VOUT) to keep the MOSFET saturated, thereby preventing possible current flow (see Figure 1).


Figure 1: Simplified hot-swap circuit

The first thing to consider for the FET is to choose the appropriate breakdown voltage, typically 1.5 to 2 times the maximum input voltage. For example, a 12V system is typically a 25V or 30V FET, while a 48V system typically has a 100V or, in some cases, a 150V FET. The next consideration should be the safe working area (SOA) of the MOSFET, such as a curve in the datasheet. It is particularly helpful in indicating how MOSFETs affect thermal breakdown during short-term power surges, as opposed to being absorbed in hot-swap applications. Since the Safe Operating Area (SOA) is the most important criterion for proper selection, please refer to the MOSFET Data Sheet - SOA Diagram, which details how TI performs measurements and then generates the SOA of the MOSFET shown in the device data sheet.


The key question for the designer is how much of the maximum inrush current the FET can withstand (or is expected to limit to the output) and how long the surge will last. With this information in mind, it is relatively straightforward to find the corresponding current and voltage differences on the SOA plot of the device datasheet.


For example, if the design input voltage is 48V and you want to limit the output current to less than 2A within 8ms, the designer can refer to the 10ms curve of the CSD19532KTT, CSD19535KTT, and CSD19536KTT SOA (Figure 2), and conclude that the latter two devices may work. And CSD19532KTT will not work. Since the CSD19535KTT already has enough headroom, the more expensive CSD19536KTT may provide excessive performance for this application.


Figure 2: SOA for three different 100V D2PAK MOSFETs

The ambient temperature is assumed to be 25 ÌŠC, as in the case of measuring SOA on the data sheet. Since the final application may be exposed to a hotter environment, the SOA derating must be scaled according to the ratio of ambient temperature to the maximum junction temperature of the FET. For example, the final system's maximum ambient temperature is 70 ÌŠC, and Equation 1 can be used to degrade the SOA curve:


In this case, the CSD19535KTT's 10ms, 48V capacity will drop from ~2.5A to ~1.8A. It is concluded that a particular FET may no longer be suitable for the application, so the designer should re-select the CSD19536KTT.

It is worth noting that this derating method assumes that the MOSFET is just malfunctioning at the maximum junction temperature, although this is usually not the case. Assuming that the failure point measured in the SOA test actually occurs at 200 ÌŠC or any other higher temperature, the calculated derating will be closer to uniformity. That is to say, the calculation of this derating method is not a conservative algorithm.


The SOA will also determine the type of MOSFET package. The D2PAK package can accommodate large silicon chips, so they are very popular in higher power applications. The smaller 5mm x 6mm and 3.3mm x 3.3mm quad flat no-lead (QFN) packages are better suited for low power applications. To withstand surge currents less than 5 - 10A, FETs are typically integrated with the controller.


Here are a few points to note:


When working with hot-swap applications, designers can use the same SOA selection process for any FET operation in the saturation region, even for OR-ing applications, Power over Ethernet (PoE), and low-speed switching applications (such as motors) Control) Using the same FET selection method, a fairly high overlap of VDS and IDS occurs during MOSFET turn-off.


Hot-swap is an application that tends to use surface mount FETs rather than through-hole FETs (such as TO-220 or I-PAK packages). The reason is that the short pulse duration and the heat generated by the thermal breakdown event are very limited. In other words, the capacitive thermal resistance element from the silicon junction to the outer casing prevents heat from being quickly lost to the board or heat sink to cool the junction. The function of the chip size - the junction-to-case thermal resistance (RθJC) is important, but the function of the package, board and system thermal environment - junction to ambient thermal impedance (RθJA) is much smaller. For the same reason, it is difficult to see the heat sink for these applications.


Designers often assume that the lowest resistance MOSFET in the catalog will have the strongest SOA. The logic behind this is that the lower resistance in the same silicon production usually indicates a larger silicon chip inside the package, which does result in better SOA performance and lower junction-to-case thermal impedance. However, as the silicon iterations increase the unit area resistance (RSP), silicon wafers also tend to increase battery density. The denser the cell structure inside the silicon chip, the more susceptible the chip is to thermal breakdown. This is why older generation FETs with higher resistance sometimes have better SOA performance. In short, it is very necessary to investigate and compare SOA.


Please find out more about the various hot-swap controllers on the TI website. Tables 1-3 at the end of this article highlight some of the devices used for hot swap, which provide partial reference values ​​for SOA functionality.
See the MOSFET Options blog series for more information.


Table 1: MOSFETs for 12V Hot Swap

MOSFET

VDS(V)

Package

Type RDS(ON)(mΩ)

SOA rated current (A) @ 14V VDS

@ 10V VGS

1ms

10ms

CSD17575Q3

30

SON3.3x3.3

1.9

4.5

2

CSD17573Q5B

30

SON5x6

0.84

8

4.5

CSD17576Q5B

30

SON5x6

1.7

8

4

CSD16556Q5B

25

SON5x6

0.9

25

6

CSD17559Q5

30

SON5x6

0.95

30

14

CSD17556Q5B

30

SON5x6

1.2

35

12

CSD16401Q5

25

SON5x6

1.3

100

15

CSD16415Q5

25

SON5x6

0.99

100

15


Table 2: MOSFETs for 24V Hot Swap

VDS(V)

Package

Typ RDS(ON)(mΩ)

SOA rated current (A)

@ 30V VDS

@ 10V VDS

0.1ms

1ms

10ms

100ms

CSD18531Q5A

60

SON5x6

3.5

28

9

3.8

0.9

CSD19502Q5B

80

SON5x6

3.4

30

9

3.2

1

CSD18532NQ5B

60

SON5x6

2.7

100

8.6

3

1.9

CSD18540Q5B

60

SON5x6

1.8

105

13

4.9

2.2

CSD19535KTT

100

D2PAK

2.8

130

18

5.1

3

CSD19505KTT

80

D2PAK

2.6

200

18.5

5.3

3.4

CSD18535KTT

60

D2PAK

1.6

220

twenty one

6.1

4.1

CSD18536KTT

60

D2PAK

1.3

220

31

9.5

5

CSD19506KTT

80

D2PAK

2.0

310

29

10

5.3

CSD19536KTT

100

D2PAK

2.0

400

34

10.5

5.4


Table 3: MOSFETs for 48V Hot Swap

VDS(V)

Package

Typ RDS(ON)(mΩ)

SOA rated current (A) @ 60V VDS

@ 10V VDS

0.1ms

1ms

10ms

100ms

CSD19531Q5A

100

SON5x6

5.3

10

2.7

0.85

0.27

CSD19532Q5B

100

SON5x6

4.0

9.5

3

1

0.33

CSD19532KTT

100

D2PAK

4.6

41

3.3

0.8

0.5

CSD19535KTT

100

D2PAK

2.8

46

6.1

1.9

1

CSD19536KTT

100

D2PAK

2.0

120

11

3.7

1.9

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