LPC interrupt processing summary
Recently, I have read the literature on the LPC interrupt process. As a beginner, this content is still very different from other processors. For example, the Samsung S3C4510B has a totally different concept in interrupt handling. Personally feel that LPC is more difficult, and many places feel it is in line with the specifications of ARM, the following specifically talk about the relevant content.
Basic knowledge: LPC2294's EXT interrupt is divided into three categories, including FIQ, Vectored IRQ, non--Vectored IRQ, among which FIQ has the highest priority and non--Vectored IRQ has the lowest priority. The system provides a total of 27 Interrupt sources, and these 27 interrupt sources have been fixed number, but note that this number does not have any relationship with the priority, not the higher the priority of the number in the front, as described below.
The key content: two sets of control channels,
The first set: In the ARM architecture, there are originally defined SWI, FIQ, IRQ, etc., and the interrupt control bits of these interrupts have already been defined. That is, in the CPSR register, this register contains an I bit and an F bit. , I bit is used to control the IRQ interrupt switch, F is used to control the FIQ switch, but it is worth noting that the CPSR read and modify in user mode can not be completed, must be through the SWI instruction to enter the privileged mode Can be modified.
The second set: In the LPC SFR (Special Function Registers), a set of registers is also provided to control the corresponding interrupts. This set of controllers is called the VIC register (all of which start with the VIC). The reorganized register includes all the The functions related to interrupts such as setting, opening, and sorting are only to separate out some of the functions corresponding to the external interrupt pins and handled by the EXT register. Therefore, it is very important to master the registers of this series.
The relationship between the two: just open the FIQ in the second set of control channels, IRQ interrupt is not enough, if the ARM core does not open the interrupt, the entire system will not be interrupted, so the common practice is this: First The second set of channel control content is handled well, and then through the SWI software interrupt instruction, the ARM processor mode is switched to privileged mode, in the privileged mode, the CPSR "read-modify-write-back" operation, will be interrupted Open, then return to user mode.
The specificity of LPC's interrupt: There is no difference between the FIQ interrupt and the normal ARM specification. That is, when the interrupt is generated, the instruction jumps to 0x0000001C to start execution. This is no doubt. However, the IRQ response process is different. Look at the following section of code. This is a partial byte written in the head of the program:
Reset
LDR
PC, ResetAddr
;// 0x00000000,Reset
--->Supervisor Mode
LDR
PC, Und_Addr
;// 0x00000004,Undefined InstrucTIon
--->Undefined Mode
LDR
PC, SWI_Addr
;// 0x00000008, Software Interrupt
--->Supervisor Mode
LDR
PC, PAbort_Addr
;// 0x0000000c, Abort(Prefetch)
--->Abort Mode
LDR
PC, DAbort_Addr
;// 0x00000010, Abort(Data)
--->Abort Mode
DCD
0xB9205F80
;// 0x00000014,Reserved
--->
LDR
PC, [PC, #-0xFF0]
;// 0x00000018,IRQ
--->IRQ Mode
LDR
PC, FIQ_Addr
;// 0x0000001c, FIQ
The instruction is "LDR
PC, [PC, #-0xFF0]" is very special, it does not jump to the entrance of the IRQ interrupt routine, but performs a post-computation assignment to the PC. Here is the reason for this. In the LPC series, IRQ The response process, the program's entry address is not directly written in this statement, but placed in a register, this register is: VICVectAddr, its address is 0xFFFFF030, and now it is very clear, in the implementation of the statement "LDR
PC, [PC, #-0xFF0]â€, the PC's value has become the address of the second statement following the statement, that is 0x00000020, and 0x00000020-0xFF0, a borrow occurs, the result is exactly 0xFFFFF030, That is to say, through this simple operation, the PC jumps to the address contained in the register VICVectAddr, thus simply completing the IRQ jump.
Of course, there are more than one IRQ interrupt source, and there are more than one interrupt service routines. The value of this register is automatically updated, and another set of registers, VICVectAddr0 to 15 (followed by numbers), places the IRQ 16 interrupt source addresses in corresponding The location (priority and other contents have additional registers to control, not much to say here), when the IRQ interrupt occurs, the hardware automatically passes a corresponding address in the corresponding VICVectAddr0 to 15 to the VICVectAddr register. This process does not require Let's program to achieve.
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