Because Verilog is a hardware description language, when writing the Verilog language, you must first have a concept of how the module should be implemented on the hardware, rather than how the compiler interprets the module. For example, in deciding whether to use the reg definition. When you ask yourself whether the register is physically present, if so, what is its clock? What is the D terminal? What is the Q end? Is there a clear and set? Synchronous or asynchronous? Another example of the three-state output problem discussed above, the first thing that should come up is to add a three-state gate after the output of the register, rather than how to let the compiler know that it is "assigned" to a signal that is tri-stated. Similarly, there is no concept of "compilation" in Verilog, but only a comprehensive concept.
The purpose of writing a hardware description language is to synthesize, so if you want to write well, you need to have a deep understanding of the synthesizer, so that the code written is efficient.
Some things are completely meaningless. Like some programs in some books, they are completely incomprehensible. For example, a program that generates a 10ms square wave, and what #10 ~clk, such a statement hardware is impossible to do. It is used for verificaTIon, not comprehensive. Teacher Zhang’s book is good for junior textbooks, but it is not enough to master verilog through it. A senior engineer who had contacted the Motorola Design Center in Suzhou, he advised: When using verilog to describe the circuit, it must be clear about the circuit it implements. Many people only care about the verilog language and are not familiar with the circuit it implements. Is not designed to have a good circuit
Generally speaking, when writing verilog code, the structure of the whole hardware should be very clear. It is better to have a detailed circuit drawing, timing problems, etc. should be considered clearly. You can write the code directly by looking at the picture.
You should know that Verilog was originally invented for simulation. The incomprehensible Verilog statement is also very important. Because in the actual design of the circuit, in addition to implementing a synthesizable module, you need to know how its peripheral circuit is. And my circuit and these peripheral circuits can work in harmony. These peripheral circuits can be implemented with non-integratable statements regardless of how it is implemented. Because they may already exist, I only use it. To simulate. Therefore, when writing verilog, you should first make clear whether I use it to simulate or synthesize. If it is used for synthesis, it must be strictly used synthesizable statements, and different ways of writing may be produced. The circuit will be very different. At this time, we must understand some of the verilog synthesis methods. As I said before, there must be a hardware concept in my mind. Especially when comprehensively reporting errors, I have to think about my way of writing. Can not be achieved with hardware, verilog is not C, after all, a lot of writing is not possible. If this module is only used for simulation, it is much more flexible, then you don't have to Care about the hardware implementation. As long as its syntax, realize the function you want on the line.
Some netizens said that the problem with #10 clk=~clk, although this statement is not synthesizable, but in doing simulaTIon and verificaTIon is often used in estbench to generate a clock signal. For example, the large-capacity memory that is often used is generally not implemented on the chip. At this time, an unsynthesizable module is also needed. Mengxy is convinced.
The purpose of the module we designed is to be able to synthesize functionally correct, standard-compliant circuits. I think this is an iterative process, just like we have to specify the pre-simulation, the integrated simulation, and the post-simulation in the design flow. Simulation is a very important means of verifying our design. And the verilog statements that look boring will play a big role at this time. I think that the brothers who have used verilog_xl should have a deep understanding. The operation in verilog_xl can be done with the system command in verilog. I also have a deep understanding of the recent application. Many companies are interested in whether you are considering TIming, architecture, DFT, etc. when writing code. This also means that any statement in verilog is very important.
Before writing the code, you must have a clearer concept for the specific hardware. But it is too exaggerating to complete the synthesizable code once. Verilog's top-down design method starts from behavioral modeling, and the function verification is later turned to Comprehensive model. Too much care and synthesizable makes the initial design become too tired
I agree with this view. When designing a logical structure, the comprehensive factor is to be considered, but there are many things that cannot be considered too carefully. It is not too tight when the design is designed, such as delay, area, etc. After the synthesis, the margin of optimization will be small, and it is not good for design optimization. If the delay and area requirements are not very tight, in fact, the behavior level of code writing is optimized by using comprehensive tools. I heard that there is a well-known company, I believe that the optimization ability of the integrated tools, never do the integrated simulation, hehe. Of course, if the area and delay requirements are very high, it is best to write the bottom of the code, When calling a library unit, you should also consider the factors of its area and delay.
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