Figure 1 SDH equipment clock functional block diagram of ITU-T Recommendation G.783 specification
The purpose of the design is ultimately to achieve the product, but the product implementation includes both design and production. From the perspective of the overall designer, it is naturally desirable to have a highly reliable clock system whose performance meets the requirements of the ITU-T G.813/G.8262 specification and whose functions conform to the block diagram shown in Fig. 1, so that it can be a synchronous device. The stable work provides a high-quality system master clock, taking into account the implementation cost of the entire device. This undoubtedly puts very high demands on both system engineers and clock technicians: it is necessary to consider performance and functional reliability of the master clock, as well as how to ensure the distribution quality of the master clock in the system equipment, and also to consider the clock. The overall efficiency of the system and ultimately the production of the final equipment.
This article only makes detailed analysis and discussion on several types of implementation schemes of the synchronous device timing generator SETG, which is the core component of the synchronous device clock system. It is hoped to provide engineers with some ideas for reference, and it can comprehensively balance the clock when related designs are carried out. Performance, design efficiency, product cost, etc., enable the design to be implemented with high efficiency, and lay a solid and reliable foundation for the further realization of a complete clock system.
From the current situation, there are mainly three types of solutions for SETG, the timing generator for synchronous equipment:
1. Self-contained design
For simplicity, SETG is first a phase-locked loop with frequency and phase retention. The so-called hold function is that when the input reference source of the phase-locked loop is interrupted, the output frequency and phase of the phase-locked loop are maintained at the instantaneous position before the reference source is interrupted, and the general phase-locked loop does not have this capability. Implementing the hold function is also key to the SETG design. Therefore, a variety of different design solutions can be generated around the method of maintaining the function. For example, on the basis of an analog phase-locked loop, ADC acquisition and DAC reduction voltage control voltages are used to achieve a hold function; a digital phase difference output using a digital phase detector connects a DAC to generate a voltage-controlled voltage to achieve a hold function, and so on.
Prepare and set up a special clock development department, use FPGA/EPLD, DSP/CPU, DAC/ADC and other components, and then select the appropriate voltage-controlled crystal oscillator to develop and design the corresponding program. This is early in the development of SDH technology, because there are no other options to choose from, equipment manufacturers have to experience. This requires first enough time, but also has considerable technical capacity of R & D personnel. Because SDH equipment clock technology involves phase locked loop, crystal oscillator, communication system and computer and other technical fields. Needless to say, the requirements for hardware development and software development are very high. Developers must have a deep knowledge of software and hardware technologies. They must also be equipped with special clock test instruments and meters, be familiar with relevant test and measurement technologies, and then undergo repeated long-term iterations. The exploration and accumulation of experience will eventually complete the design of synchronous equipment clocks with performance indicators that meet the requirements of technical specifications and are reliable and practical. Here, due to the choice of different implementations of the hold function, the SETG circuit design may result in a large variety of component types, quantities, and costs.
Based on the results of this scale of human and material resources and time investment, we can have in-depth understanding of the technical details of synchronous equipment clocks, and can also make targeted changes to the design scheme according to the needs of different product projects, at the expense of increasing the development workload. Functional and cost optimization. For example, depending on the project, a new type of voltage-controlled crystal oscillator is used to adapt to special requirements, but this requires retesting and verification. In addition, it is hard for equipment manufacturers to have other benefits. From the point of view of production and testing, due to its professional breadth and strong technical capabilities, equipment manufacturers need to bear the corresponding technical risks; in terms of cost, in addition to normal raw material procurement, production testing, and material loss, production management costs are generally maintained. The cost of these senior technicians is also a big expense.
For equipment manufacturers who have mastered the SDH equipment clocking technology earlier, there is no doubt that they have achieved certain advantages in the competition. After years of development, there have been professional manufacturers offering different types of synchronous device clock solutions to help users complete clock designs more efficiently and conveniently. As an indispensable general technology for related communication equipment manufacturers, the SDH equipment clock has no technical barriers when the SDH industry just started. Nowadays, the main problem facing the manufacturers of communication equipment is that it is necessary to consider how to reduce costs and develop more competitive products under the premise of ensuring product quality.
2. Outsourcing clock module
The off-the-shelf synchronous device clock module provided by outsourced professional manufacturers is the most convenient and quick way to implement SETG.
The clock module is actually a professional manufacturer that uses its accumulated expertise and experience in phase-locked loops, crystal oscillators, etc. to integrate component circuit designs into highly reliable component designs, and to use specialized equipment and standardized production processes. Batch commissioning production is a mature module product. The difference between the self-prepared clock design scheme and the professionalization of the module design and the standardization of production debugging are the values ​​of professional division of labor and professional manufacturers.
As with most self-contained solutions, in terms of clock quality, because of the buffer output or frequency-divided output of the high-stability crystal oscillator, this direct-output clock has the quality of a crystal oscillator and can meet the communication system requirements required by high-performance specifications. Different from the self-contained clock design, all the SETG's performance and key functions are implemented within the module. The production debugging process is also completed within the factory. The external interface of the clock module is greatly simplified, showing a relatively standard and standard. User-friendly use features. Companies such as CONNOR WINFIELD, RARALON and others have provided such synchronous device clock modules and are relatively early manufacturers of such products. There are also professional manufacturers in China to provide compatible clock module products. Their products have a certain amount of use abroad and domestic manufacturers also use them.
For manufacturers who do not have the energy to design their own dedicated clock solutions, or because the quality of the clock directly output by the non-crystal oscillator does not meet the requirements, or simply do not like other complex solutions. At this time, using a simple and convenient clock module becomes a reasonable choice. Here, since the performance indicators of the clock have been guaranteed by the module, only a dozen pins are packaged, and a data sheet of about ten pages makes the module easy to use, and the workload of related technicians is greatly reduced. System designers do not have to worry about the clock performance and design cycle of the system, so they have more time and energy to optimize the overall performance of the device and design more competitive communication products. If module prices can also be accepted, this is the situation that equipment manufacturers want to see most. But unfortunately, even before the domestic manufacturers of the clock module is also high prices, ordinary users simply can not afford, can only look "block" sigh!
3. Dedicated chip + crystal oscillator
The implementation of the last type of SETG is a clock-specific chip plus an external crystal oscillator provided by an IC manufacturer as a frequency standard. There are already several IC manufacturers on the market offering chip + crystal oscillator solutions with high mid-to-low price. Such as the earlier SEMTECH, and more recent MAXIM. From the perspective of ease of use and cost-effectiveness, this approach lies between a self-contained design solution and the use of off-the-shelf clock modules. This was the best and only option for equipment manufacturers who could not stand the risk of their own development and the price of finished clock modules.
Professional IC manufacturers use the design technology of analog and digital hybrid integrated circuits to give full play to the characteristics and advantages of integrated circuits. The development includes digital phase-locked loop DPLL, analog phase-locked loop APLL, microprocessor interface I2C/SPI, and multiple clock inputs. The output adapter interface and so on are as full-featured as possible. Then, a high-stability standard crystal oscillator is disposed outside the chip to provide a reference frequency for the chip, which basically constitutes the main body of the synchronous device clock system. Compared with self-contained design solutions, although the convenience of application is not very good, it is already clearly dominant. If the clock module scheme is compared with the past, the application convenience is poor but the cost is advantageous.
The problem with the ease of application is first of all the complex use of the chip, which is also a side-effect of the chip while demonstrating its versatility. Although many of the features required for a specific design are not used, due to the powerful features of the chip and many pins (tens or hundreds or even more than two hundred), they generally have hundreds of pages of data manuals. One or even hundreds of control registers need to be correctly configured by the user through software. The configuration includes free oscillation frequency correction, noise bandwidth setting, reference source frequency setting and so on. Incorrect configuration affects the indicator, while it does not work properly. Some low-end chips, at the expense of integrated circuit functional integration, reduced functional modules and other means to reduce the cost, but also simplify the use of some difficulties, but resulting in a lack of functionality or even a drop in performance, making the chip can not Meet the needs of multiple levels of users. Secondly, the choice or improper use of an external crystal oscillator as a standard frequency and performance guarantee can seriously affect the final performance index. Increasing the crystal oscillator as a key device will inevitably bring about production and management tasks and costs. In addition, no matter which kind of chip, the user must select the appropriate external crystal oscillator on the basis of complete digestion of the chip data, and at the same time, he/she masters the related production and test technologies, and may have confidence to ensure that the clock performance indicators can be reliably realized. . Comparing self-contained design solutions, although the requirements for designers are greatly reduced, they still need to have considerable standards. The difference is that you don't have to worry too much about clock performance. After all, chip vendors already have a commitment, provided they are familiar with the chip data plus the correct production test methods.
The chip + crystal oscillator solution also has an inherent deficiency: the high-stable crystal oscillator here only provides a standard frequency, and the output master clocks that are actually supplied to various frequencies of the communication system are generated by integrated circuit oscillators inside the chip and integrated. The clock quality of the circuit oscillator is inferior to the clock quality directly output by the crystal oscillator, such as the jitter index of the clock. Therefore, the output clock of the chip + crystal oscillator scheme cannot be used in high-performance devices that require strict performance unless the phase-locked loop based on the crystal oscillator is used to smoothly filter the output clock.
In short, the SETG implementation of the chip+crystal oscillator also has similar development risks and production costs as the self-prepared design, but the degree is different.
At present, the domestic situation is that only a few system equipment manufacturers who are earliest involved in the SDH technology field are still using self-designed clocking schemes. The vast majority of others are choosing the chip + crystal oscillator solution, and as an ideal clock module solution, Due to the fact that there is no price-to-price ratio for a generally accepted product, the existing clock module is also expensive due to its high cost.
Comparison of various types of plans:
Through the above analysis, it can be seen that, ideally, the modular design concept is adopted, and the synchronous device clock is designed as a universal module product with a series of standardization, function standardization, and application simplification, and the production test with complicated procedures and high technical requirements is submitted to experience. Rich specialized manufacturers to complete. The standardized series can provide equipment manufacturers with a range of functional options to suit different application needs. As a result, the system equipment manufacturers are freed from the design and production of parts that are less effective, and they concentrate on the value that can be reflected by the users of their system makers, such as the functions and performance, and even the price competitiveness of the whole machine. The promotion. This specialization should be the direction of technology development. On the basis of the above series of standardization, functional standardization, and simple application, how to use the advantage of specialization and scale to further reduce costs and provide users with cost-effective universal module products, is the efforts of professional manufacturers of modular clock products aims.
The modular design concept of synchronous device clocks should generally include the following aspects:
Series standardization: to meet a variety of common application needs, to adapt to different regions of the specifications and recommendations, specifications will be set in the input reference frequency, output clock frequency, etc. are different. SDH series (output frequency 19.44M, 38.88M, 77.76M, 155.52M optional), synchronous Ethernet series (output frequency 25M, 50M, 125M optional), both compatible series (can simultaneously output SEC and EEC clock frequency ) and switch series (output frequency 16.384M, 32.768M optional); corresponding North American specifications series; input reference standard frequency 1K, 8K, 1544K, 2048K, 16.384M, 19.44M, 25M, 32.768, 38.88M, 50M, 77.76M, 125M optional.
Functional standardization: Provides equipment clock control functions, working status information, and production test functions required for network management. It can control the switching between the three operating modes of module tracking, hold and free oscillation. The status indication includes reference source frequency indication, reference source loss indication, lock indication, hold status indication, free oscillation indication, INT alarm, etc., which can control all output terminals to enter a high-impedance state, and the reference input has adaptive multiple reference source frequencies. ability.
Application simplification: Modules work independently without complicated controls and the user interface is simple and practical. This not only improves the reliability but also reduces the user's development workload: without calibrating the nominal frequency when free running, without learning the complex register configuration, without considering the choice of the external oscillator and the related production test.
In the modular concept described above, the ability to adapt multiple reference source frequencies provides the user with maximum design convenience. Users only need to select suitable clock modules for input and output according to their designed function requirements, such as several channels of output and frequency, and frequency types of adaptive input reference sources. Then, the reference source management program of the network management can send the selected reference source to the reference input of the module, without worrying about the frequency difference of the reference source, as shown in FIG. 2 . However, all the control for the module is only the mode of operation that requires the user to select the module, such as tracking or free-running mode. Other performance indicators, such as free-running frequency accuracy, noise bandwidth, etc., are all calibrated and calibrated by the manufacturer before shipment. The clock module here has the "fool" feature that is similar to the "point and shoot camera" and is convenient for users.
Figure 2 "Idiot module" simplifies the design of synchronous device clock
In summary, the SETG implementation method of the self-provided design solution is time-consuming and labor-intensive, and the comprehensive cost is not necessarily advantageous. The designer naturally has wise decisions; the SETG implementation in the form of a clock module is due to its ease of use, reliability, and other advantages. If the price can be lowered to a reasonable position, it will be the first choice for SETG design implementation. The chip + crystal oscillator solution will occupy a special position in the market with its powerful features.
By analyzing and comparing the advantages and disadvantages, it should be possible to determine a SETG scheme that meets the requirements for high-efficiency implementation. Next, based on the reliability requirements of the overall design of the device clock system, if necessary, consider configuring the backup clock in addition to the master clock, and use the phase buffer function of the line card clock module based on the crystal oscillator. Primary and backup clocks are truly non-injured switching protection. In this way, it will be possible to design a synchronized device clock system that has excellent performance, complete functions, and satisfactory indicators in all aspects.
It has been seen that in the first half of this year, the synchronous device clock module series with the above-mentioned modular design concept features and the price can be fully accepted by the professional manufacturers have been introduced, and it is expected to completely change the clock module product price high and low. Market outlook. With a higher cost performance than clock chips and better usability than previous clock modules, it can meet the clock requirements for different device performances at the high, middle and low end.
The following are the main features of the newly introduced cost-effective synchronous device clock module:
Synchronous device timing generator SETG module compatible with SDH, synchronous Ethernet Reference source input Adaptive or manual selection of 4 frequencies (Typical values: 8K, 2048K, 19.44M, 25MHz)Two quartz crystal oscillator output clock quality (typical: 25MHz, 38.88MHz)
Performance fully complies with the ITU-T Recommendation G.813/G.8262 option 1 specification. Controls all outputs to high-impedance, high-integrity 18-pin surface-mount structures (33 x 25.4 x 8 mm3)
Single Supply 3.3V Supply, 5V Level Input Compatible
The typical values ​​given above have covered common input and output frequency points to meet most application needs. If other frequencies are required, it is also possible to select from a series of data sheets, including synchronous clock output options up to 155.52 MHz/156.25 MHz and LVPECL levels. (End of the article)
Zhejiang Casnovo Materials Co., Ltd. , https://www.casnovonewenergy.com