In the development of image processing applications, one of the easiest ways to capture or display images is to use HDMI (High-Definition Multimedia Interface). HDMI is a proprietary standard that can transmit high-definition digital video and audio data. It is supported and widely adopted by many displays and cameras. This feature makes HDMI an ideal interface standard for Zynq image processing applications.
In this article, we will introduce how to use Zynq-based HDMI transmission on different target development boards.
Figure: Arty Z7 HDMI input and output case
There are two ways to decode HDMI video based on the Zynq development board:
The external decoding (PS side) is then transmitted to the PL side through the I2C bus
Internal decoding (PL side) internal direct decoding
Figure: Zynq development board supporting HDMI
If the development board uses an external codec, you can use ADI's ADV7511 and ADV7611 to send and receive. The external HDMI codec is directly connected to the HDMI connector, and generates a TMDS signal containing image and audio data (minimal transmission of differential signals).
The I2C bus, pixel data bus, timing synchronization signal and pixel clock constitute the interface between the codec and Zynq PL (Programmable Logic). We transmit the pixel data, synchronization signal and clock directly to the PL terminal. Use the I2C controller on the Zynq PS (processing system) side to control the I2C interface, and transmit the I2C IO signal of the Zynq SoC to PL IO through EMIO.
In order to simplify the integration complexity between the codec and the PL, here are two IP cores developed by AVNET, which can be downloaded via Avnet GitHub (github.com/Avnet/hdl/tree/master/IP). In the image processing chain, they can be placed at the foremost and last end of the processing chain to connect to external codecs.
Another method is to use the internal codec located on the Zynq PL side. In this case, the HDMI TMDS signal is directly transmitted to the PL IO, and the codec is implemented with programmable logic. In order not to write such a complex codec from scratch, you can directly use the two codec IP cores provided by DIGILENT (click: http:// attachment download). Using these cores in the design means that the IO standard of the TMDS signal in the constraint file is set to TMDS_33 IO.
Note: This IO standard is only applicable to the high range (HR) IO group.
Figure: HDMI IP core mentioned in this article
In fact, not all Zynq development boards can receive and transmit HDMI signals. For example, ZedBoard only provides HDMI output. If you must use this kind of development board to receive HDMI signals, we can use the FMC interface with the FMC-HDMI daughter board to operate.
The Digilent FMC-HDMI daughter board provides two HDMI inputs, which can receive HDMI data using external and internal codecs. Among the two inputs, the first uses ADV7611, and the second equalizes the HDMI signal and transmits it directly to Zynq PL for decoding. This allows us to demonstrate how to embed internal and external codecs into ZedBoard when using external codecs for image transmission. However, here first we need to solder a jumper on J18 with an electric soldering iron, so that we can set the VADJ on the ZedBoard to 3v3 according to the requirements of the FMC-HDMI daughter board.
Picture: Zedboard + FMC-HDMI daughter board
Finally, a friendly reminder: Although we mainly discuss Zynq SoC here, the above method is also applicable to Zynq UltraScale+ MPSoC that integrates the Display Port () function~
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